APTA - Advanced Packaging Technology of America













 
Design Guidelines

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INTRODUCTION:

Intent and Scope: To establish working parameters and design standards for the optimal layout of circuits for fabrication and assembly at APTA Group, Inc.

 

Definitions:
Aspect ratio: Concerning resistor design, the length of the resistor divided by the width of the resistor (L / W), the length always being the distance between the conductor terminations.
 
Glaze: Material used for mechanical and environmental protection, or as a solder mask.
 
Substrate: The base, or foundation on which the circuit is built up and printed.
 
Through hole: A metallized via, or hole through the substrate that attaches the front side of the circuit to the back side.
 
Via: A metallized hole through dielectric material built up on the substrate that connects one layer of metallization to another.
An Overview of the Process:
Fabrication:
APTA Group fabricates circuits on ceramic substrates. These circuits may have as many as seven or more layers of conductors, or as few as a single layer of conductor. Other circuit elements such as resistors and capacitors may be added to the conductor layers. The conductor layers are separated by layers of dielectric material. The dielectric layers are either laminated tape cast dielectric, or screen printed dielectric depending on the density of the circuit. Conductors, resistors, and imbedded capacitors are all screen printed. All materials are kiln fired at 850 C to 930 C. Screen printed resistors and capacitors can be laser trimmed to achieve final values.

Assembly Procedures:
Unique APTA Group processes include:

A. High temp seal ring and heat sink attach

B. High temp lead frame attach

C. Ball grid array attach

Other APTA Group assembly processes include:

A. SMT pick & place, and reflow

B. Chip and wire assembly

C. Hand assembly

Testing:
Passive testing of unassembled substrates is done on an ATE tester. Functional testing is done per customer specifications, and is not covered in this guideline.

GUIDELINES:

1.0 Layout for Component Placement

1.1 Spacing: SMT components require a 0.020" spacing between component pads that connect to different signals. Conductor routes adjacent to solder pads need to have a 0.010" space. Tighter spacing can be negotiated.

1.2 Component pads:

1.2.1 Surface mount pads:

A. SOT23 pads will be 0.030" square.

B. Chip components such as caps and resistors will extend 0.015" beyond the end of the component, making the total configuration 0.030" longer than the component. The pad width will be 0.005" beyond the side of the component, making the pad 0.010" wider than the component width.

C. Solder pads that are located on the surface of dielectric material will have a separate conductor print of pads only. Solder pads on dielectric are double printed in fabrication to meet solderability requirements.

1.2.2 Chip and wire pads:

A. I.C. placement pads will be 0.010" wider and longer than the I.C.

B. The preferred wire bond pad size is between 0.015" x 0.015" and 0.010" x 0.010", 0.005" x 0.010" is the minimum acceptable size.

C. Wire bond pads will be located no greater than 0.120" from the I.C., and no closer than 0.015" from the I.C. pad.

D. Wire bond pads closer than 0.035" to any component will be no closer than 1.5 x the height of the component.

1.2.3 Seal rings: The preferred conductor width of a seal ring land pattern is 0.040" greater than the seal ring width, or 0.020" on either side of the seal ring. The solder print pattern is 0.020" greater than the seal ring width, or 0.010" either side of the seal ring pattern. Exposed Au within 0.020" of seal ring metal must be passivated.

1.2.4 BGA solder ball attach: Pads for 0.030" diameter solder ball attach shall be 0.023" diameter. Ball pitch may be either 0.050" or 0.060", staggered or straight. 0.025" diameter balls on 0.018" pads are available for 0.040" pitch. Other ball sizes are available.

2.0 Conductors:

2.1 PdAg and Au line widths of 0.005" are standard in our process. Line widths down to 0.003" in gold are acceptable in APTA’s print process. Line widths and spaces less than 0.003" are available with APTA’s gold etch process. Gold etch may be used when extremely precise line edges are required.

2.2 Conductor spaces down to 0.005" are standard. 0.003" spacing may be used sparingly. 0.004" Au spaces are standard.

2.3 A 0.010" wide area around the perimeter of the part should be kept free of printed circuit elements. This includes conductors, resistors, and overglazes, but does not need to include dielectrics. This area is to allow for laser scribing. The rule may be violated if incidental damage to the conductor or other circuit element by the laser scribe is acceptable.

2.4 Through holes are 0.007" in diameter. The preferred land pad size is 0.015", either square or round. A 0.012" land pad is acceptable.

2.5 If gold runs are being terminated to solder pads requiring SnPb solder, the termination area must be out of the solder area with a minimum overlap of 0.005", and be covered by glaze with no less than 0.005" between solder pad side of termination and edge of glaze. This is to allow for the +/- 0.002" registration tolerance between layers.

2.6 Au and PtAu conductors shall not terminate on PdAg filled through holes, but must terminate at least 0.020" from the center point of the through hole.

3.0 Resistors:

3.1 Tolerances are based on a one square resistor. The numbers are stated in inches. These numbers are not absolute in any sense, but are based on good test results. Tolerances as low as 0.1% are achievable in our process. Our standard minimum size is 0.020" wide. This rule may be broken only after consultation. In general, the design practice should be to make a resistor as large as possible. This is done to reduce process variability, and to reduce laser trim time and cost.

  0.50% 1% 2% 5% 10% 20%
1 ohm square 0.03 0.03 0.02 0.02 0.015 0.01
5 ohm square 0.03 0.03 0.025 0.02 0.015 0.01
10 ohm square 0.03 0.025 0.025 0.02 0.015 0.01
50 ohm square 0.03 0.025 0.025 0.02 0.015 0.01
100 ohm square 0.03 0.025 0.025 0.02 0.015 0.01
1k ohm square 0.03 0.025 0.025 0.02 0.015 0.01
5K ohm square 0.03 0.025 0.025 0.02 0.015 0.01
10K ohm square 0.04 0.03 0.025 0.02 0.02 0.01
50K ohm square 0.05 0.04 0.035 0.03 0.025 0.015
100K ohm square 0.05 0.04 0.035 0.03 0.025 0.015
500K ohm square 0.06 0.05 0.04 0.035 0.03 0.02
IM ohm square 0.07 0.06 0.05 0.04 0.035 0.03
5M ohm square NO NO 0.07 0.065 0.06 0.05
lOM ohm square NO NO 0.08 0.075 0.065 0.05

3.2 Square count/aspect ratio: Aspect ratios of 0.2 to 5 are reasonable for any given range. This is not absolute. For example, a 10K ohm square resistor decade can be extended out to a square count of 10 if needed to eliminate a single 100K resistor print. Top hat resistors are also acceptable for extending the range of a given ink, or for functional trims. Serpentine resistors may also be used for extending the range of a resistor. If a linear trim would be advantageous, a shunted resistor may be used.

3.3 Resistor terminations: The standard overlap of a resistor onto the conductor is 0.010". This may be shortened to no less than 0.005". The conductor termination should be a minimum of 0.010" wider than the resistor width, allowing for 0.005" on either side of the resistor.

3.4 Resistor probe pads and locations: All resistors need to have probe locations for laser trimming. Additionally, low value and tight tolerance resistors need to have specific probe locations noted. This would include any resistor that has a tolerance equal to or less than 1 ohm, or a conductor trace with a resistance that exceeds the tolerance of an attached resistor. The probe locations may be a component mounting pad or an adjacent conductor area. The minimum probe pad size is 0.015" (either circle or square). Multilayer structures may not have obvious probe locations. If this is the case, these locations should be noted.

3.5 Wattage: In general, wattage is derated to 50 watts per square inch to factor in laser trimming; however, 100 watts per square inch material is available upon request.

3.6 T.C.R.: T.C.R.'s of +/- 100ppm are standard on PdAg and Au terminations. A +/- 50ppm T.C.R. can be achieved, but may be design dependent. Resistors terminated on PtAu may have a greater T.C.R.

4.0 Capacitor Layout:

4.1 The basic formula used to define capacitor plate size is: C = 0.225KA/th C = capacitance K = dielectric constant A = area of overlapping conductor plates th = the thickness of the dielectric between the plates

Note: Capacitance is expressed in picofarads, and all dimensions are in inches.

4.2 Dielectrics constants available are: A. K=4.5 B. K=8.0 C. K=25 - 500 (blendable series) D. K=2000 - 10000 (The actual K is process dependent, K = 10000 on ceramic with PdAg plates, K lowers dramatically when embedded in an MCM structure, values achieved depend on actual process steps involved.)

4.3 Capacitor tolerance: As fired tolerance depends on the area of the capacitor plates. A 10% tolerance will require at least an area of 0.0025 sq" for the low value materials. Capacitors less than 15pf will have an as fired value of +\- 20%. Capacitors using K = 2000-10000 will have an as fired value of +\- 20%. Capacitors can be designed to be trimmed down to value to achieve tighter tolerances.

4.4 Types of capacitors:

4.4.1 Capacitors printed on the surface of a substrate will have a typical thickness of 0.0015" to 0.002". Capacitors printed into tape cavities will have a typical thickness of 0.0025". Capacitors made by using tape as the dielectric will have a typical thickness of 0.0025" to 0.003".

4.5 Design guidelines for capacitors:

4.5.1 Cavities for imbedding capacitors are as noted in 6.2 below.

5.0 Printed Multilayer Dielectric:

5.1 Via size = 0.012" either circle or square.

5.2 Via fill = 0.012" same shape as the via.

5.3 Via land pad (the pad that would go on top of the via fill) = 0.015" either square or round.

5.4 0.010" space between a conductor and an adjacent via land pad.

5.5 Routing beneath the active area of a trim resistor is not acceptable. The laser trim can expose underlying metallization.

5.6 Stacked vias are allowed. Vias cannot be stacked over through holes, but should be offset by 0.010" from center of through hole.

5.7 Cross over:

A. Conductor spacing at the point where the cross over conductor drops off the dielectric crossover must be 0.010" or greater.

B. If used, via size = 0.012" (either circle or square.)

C. If used, via fill = 0.012" same shape as the via.

D. Via land pad (the pad that would go on top of the via fill) 0.015" either square or round.

E. 0.010" space between a conductor and an adjacent via land pad.

F. If resistors are placed on top of the dielectric, then routing beneath the active area of a trim resistor is not acceptable. The laser trim can expose underlying metallization.

G. Stacked vias are allowed. Vias cannot be stacked over through holes, but should be offset by 0.010" from center of through hole.

6.0 Tape on Substrate Technology Specific Guidelines:

6.1 Drilled tape guidelines:

A. Via size = 0.006" circle is standard, holes down to 0.002" are available upon request.

B. Via fill = 0.002" larger than via.

C. Via land pad (the pad that would go on top of the via fill) 0.005" larger than the via (either square or round). Smaller lands can be negotiated.

D. Space between conductor and adjacent via land pads = 0.007".

E. Routing beneath the active area of a trim resistor is acceptable, but should be done sparingly.

F. Stacked vias are allowed. Vias can be stacked over through holes.

G. All tape designs will include a perforated scrap edge no less than 0.050" from perimeter of active array and no closer than 0.050" from edge of substrate.

6.2 Recessed tape on substrate guidelines (Cavities):

A. Cavities may be designed on any layer. Cavities may not be buried by a solid layer, but must continue to the surface.

B. Due to material loss, cavity edge should be designed with 0.005" extra material. Example: A cavity that needs to be .1"x.1" on the finished product should be designed as 0.095"x 0.095".

C. Each layer that has identical cavities will be designed to increase the cavity size by 0.005" from each edge of the previous layer.

D. Space between conductors and cavity edges = 0.015" on finished product, for any given layer.

7.0 Passivation:

7.1 Green glaze cannot be used with water based SMT cleaning systems. Select either polymer glaze or a high temp glaze instead of green glaze if a water based SMT cleaning system is used.

7.2 If laser trimmed resistors are placed under surface mount components, a polymer glaze must be placed over them after laser trim to protect the trim kerf.

7.3 High temp glazes cannot be placed over printed resistors, but need to be kept 0.010" from the perimeter of the printed resistor.

8.0 Ceramic Dimensional Tolerances:

8.1 Layer to layer alignment registration tolerances shall be +/- 0.002". This applies also to "front to back" registration. Alignment to the ceramic is dictated by the ceramic tolerances as noted in 8.2.4 and 8.2.5. Print registration tolerances to a laser scribed substrate edge are non-cumulative, while print registration tolerances to green scored ceramics are cumulative.

8.2 Ceramic tolerances:

8.2.1 Ceramic camber max. 0.003"/inch. Precision ground substrates can be provided.

8.2.2 Ceramic surface finish max. 30 micro inches for 96% Al2O3, and 5 micro inches for 99% Al2O3.

8.2.3 Ceramic thickness is within +/- 10% of stated thickness.

8.2.4 Ceramic “as fired” edge X/Y dimensional tolerance is +/- 1%. 8.2.5 Ceramic scribed edge X/Y dimensional tolerance is 10% of the substrate thickness. Tolerances for arrays are non-cumulative. 8.2.6 Laser machined X/Y dimensional tolerance is +/- 0.001" from a referenced datum.

8.2.7 Laser drilled hole placement is +/- 0.0005" from a referenced datum.

8.2.8 Laser drilled hole diameter tolerances are:

A. Laser machined holes greater than 0.015" in diameter are +/- 0.00I” from the laser exit side (usually the back side) and +/- 0.002" from the entrance side of the ceramic.

B. Laser drilled holes less than 0.015" in diameter are +/- 0.001" from the exit side of the ceramic. The entrance side will vary depending on the thickness of the ceramic. Example: A 0.040" ceramic will typically have a 0.010" diameter entrance with a 0.007" exit for a 0.007" mil through hole.

9.0 Array Specifications:

9.1 Substrate dimensions:

9.1.1 Standard sizes are: A. 2.062" x 2.062" B. 3.3" x 3.3" C. 3.5" x 3.5" D. 4.5" x 4.5" E. 7.0" x 5.0"

9.2 Scrap edge:

9.2.1 Preferred = >0.15" 9.2.2 Minimum acceptable = 0.10"

9.3 Standard three pin alignment marks:

9.3.1 Pin reference points. The values listed are for substrate 0,0 datum coordinates, and are not to be confused with pin center coordinates. See Detail reference numbers.

Substrate size:      
  Pin # X-Coord: Y-Coord:
2.062x 1 +0.000" +1.031"
  2 -0.412" +0.000"
  3 -1.680" +0.000"
3.3x 1 +0.000" +1.650"
  2 -0.660" +0.000"
  3 -2.683" +0.000"
3.5x 1 +0.000" +1.750"
  2 -0.700" +0.000"
  3 -2.845" +0.000"
4.5x 1 +0.000" +2.250"
  2 -0.900" +0.000"
  3 -3.655" +0.000"

9.3.2 Standard distance from substrate edge to registration mark edge = 0.015". Any deviation from standard distance is to be specified and noted on fabrication drawings.

10.0 Test Data Requirements: The displayed format is the ideal format required for testing MCM and other complex circuits:

NET NAME COMP PIN   X Y Z
GND U1 1 385 453 0
N001 U1 8 365 453 0
VCC U1 10 455 123 0
  Component pin # Pad location Pad distance
from substrate

10.1 The important information is:

A. Net name
B. Component name
C. Pin#
D. Coordinate locations

10.2 The specific order of the columns may vary. The data should be saved in either ASCII file format, or in an agreed upon spreadsheet format.

10.3 Also required for testing is a drawing showing component placement with pin designators and probe pads. We hope these guidelines provide you the information that is required. If more information is needed please contact APTA directly.

Material Specifications

Dielectrics
  Dielectric Constant Minimum Thickness Voltage Breakdown Df Thermal conductivity Insulation resistance TCC
Printed 8 37 microns+\-2 1000 V/25 microns <0.4% 2.5-3.0 W /m / C >1012 ohms na
Std tape 8 75 microns+\- 10% 1800 V/25 microns <0.5% 2.5-3.0 W /m / C >1012 ohms na
Low K tape 4.5 75 microns+\- 1500 V/25 microns <0.4% 2.5-3.0 W /m / C >1012 ohms na
High K printed* 20-270 37 microns+\-2 500 V/25 microns .06-.4% na >1011 ohms 300
High K printed** 1000-10000 37 microns+\-2 300 V/25 microns .5-2% na >1010 ohms ***
* Df goes up with each higher K material. ** Actual K depends on process conditions.
***TCC graph available on request.

Conductors***:
  Sheet Resistivity Thickness Wire Bond Solder**
Au 2-4 milli ohm sguare 10 microns +\-2 Au, Al Lead-Indium;
Ag* 1-3 milli ohm square 14 microns +\-2 Au, Al Sn62
PdAg* 2-4 milli ohm square 12.5 microns +\-2 Au, Al Sn62
PdAg* 20-30 milli ohm square 12.5 microns +\-2   Sn62
PtAu 40-55 milli ohm square 12.5 microns +\-2   Sn62/Sn63
* Solder leach resistance increases with sheet resistivity
**Low temp solders are shown. Higher temp solders are also usable.
***Other conductors formulations are available on request.

Resistors*
  TCR Watt/in2 Fired tolerance** Std trimmed tolerance Max trimmed tolerance
1 ohm sq 200ppm +\- 100 20% 1% .1-.5%
10-l00K ohm sq 50ppm +\- 200 20% 1% .1-.5%
1M ohm sq 100 ppm+\- 200 20% 1% .1-.5%
10M ohm sq 150 ppm +/- 100 25% 5% 2%
* Thermistor material available on request
** 10% fired tolerance may be available based on design.

Substrates
  Flexural strength Dielectric K Voltage breakdown Thermal conductivity TCE Df
96% AIO2 46000 psi 9.2 800 V / 25 microns 25 W /m / C 6.9 0.03%
99%AIO2 65000 psi 10 800 V / 25 microns 25 W /m / C 7 0.03%
99%BeO 33000psi 6.4 800 V / 25 microns 255 W /m / C 7.1 0.01%
Beramic Z BeO 46000 psi 6.4 800 V / 25 microns 217 W /m / C 7.1 0.01%