APTA - Advanced Packaging Technology of America













 
Applications

Aerospace | Automotive | Industrial | Medical | Military | Telecom | Test and Measurement
   
Industry Segment:
Aerospace
 
Part Description: Serial Interface Module 1.2 Gbit DRAM Module
Parent Product Boeing 777 Flight Computer Spacecraft based Solid State Recorder
Electrical Design: Customer Customer
Layout: APTA APTA
Circuit Size(X-Y) (inches) 1.20x0.39 2.635x1.680
Circuit Area (Sq. Inches) 0.468 4.4268
     
Interconnect Parameters    
Substrate Technology: Multi Layer Thick Film HTCC Package
Metall Layers 5 5
Conductor Material Gold Moly-Tungsten
Typical Geometries .010 lines/.010 Spaces .010 lines/.010 Spaces
Via Sizes .012X.010 Rectangular .012X.010 Rectangular
Through Hole Size 10 mil NA
Via Quantity 261 2176
Through Hole Quantity 26 0
'Vias per Square Inch/Layer 122.6 98.3
Integrated Resistors 12 0
Integrated Capacitors 0 0
     
Component Parameters    
Bare Die 15 0
Wire Bonds 95 0
Wire Types/Sizes 1 mil Gold 0
SMT Devices 9 9 128Mbit DRAM Stacks
Smallest Passive 0805 1822
Total I/Os 123 488
Total Components per Sq. Inch 76.9 2.0
Total I/O per Sq. Inch 262.8 110.2
Silicon Efficiency    
Power Dissipation    
     
Die Protection    
Package Type HTCC Package Intergrated Sub/Package
Lid Type Flat Kovar Lid Domed Kovar Lid
Attachment Method Seam Sealed Lid Seam Sealed
     
Pin Out Parameters    
Number and Types of Leads 28 pin DIP 114 Gull Wing
     
Tests Required    
Environmental Full MIL-883 Full MIL-883
Electrical 3 Temp VLSI ATE 3 Temp VLSI ATE
Test Program Development APTA APTA
Test Fixture Development APTA APTA

 

Industry Segment:
Automotive
 
Part Description: Solid State Relay Resistor Module
Parent Product Automotive DRL Automotive A/C Units
Electrical Design: Customer Customer
Layout: APTA APTA
Circuit Size(X-Y) (inches) 0.9x0.9  
Circuit Area (Sq. Inches) 0.81 13.3
     
Interconnect Parameters    
Substrate Technology: 2 sided Single LayerThick Film 2 sided Single LayerThick Film
Metall Layers 2 2
Conductor Material Platinum Silver Platinum Silver
Typical Geometries .020 lines/.020 Spaces .030 lines/.030 Spaces
Via Sizes   0
Through Hole Size 8 mil 0
Via Quantity   0
Through Hole Quantity 31 0
'Vias per Square Inch/Layer 19.1 0.0
Integrated Resistors 18 4
Integrated Capacitors 0 0
     
Component Parameters    
Bare Die 1 0
Wire Bonds 5 NA
Wire Types/Sizes 5mil Alu/10 mil Alu NA
SMT Devices 19 4
Smallest Passive 0603 NA
Total I/Os   15
Total Components per Sq. Inch 46.9 0.6
Total I/O per Sq. Inch 0.0 1.1
Silicon Efficiency   NA
Power Dissipation    
     
Die Protection    
Package Type Leads Attached to Sub NA
Lid Type Glob Top NA
Attachment Method Auto Dispense NA
     
Pin Out Parameters    
Number and Types of Leads 3 Spade Lugs 7 Solder on Leads
     
Tests Required    
Environmental None None
Electrical Ambient Final Functional Resistance Test
Test Program Development APTA APTA
Test Fixture Development APTA APTA

 

Industry Segment
Industrial
 
Part Description: D/A Converter Motor Contoller
Parent Product Seismic Exploration Equipment Semiconductor Mfg Equipment
Electrical Design: Customer Customer
Layout: APTA Customer
Circuit Size(X-Y) (inches) 0.815x0.60 1.99x1.99
Circuit Area (Sq. Inches) 0.489 3.9601
     
Interconnect Parameters    
Substrate Technology: 2 Multilayer Thickfilm Sandwiched LTTT on Alumina
Metall Layers 7 3
Conductor Material Gold Platinum Silver
Typical Geometries .010 lines/.010 Spaces .005 lines/.005 spaces
Via Sizes .012X.010 Rectangular .006 Round
Through Hole Size 10 mil 0
Via Quantity 143 1067
Through Hole Quantity 26 0
'Vias per Square Inch/Layer 49.4 89.8
Integrated Resistors 16 0
Integrated Capacitors 0 0
     
Component Parameters    
Bare Die 10 5
Wire Bonds 115 120
Wire Types/Sizes 1 mil Gold 1 mil Gold/2 mil Gold
SMT Devices 5 66
Smallest Passive 0805 1012
Total I/Os 184 270
Total Components per Sq. Inch 63.4 17.9
Total I/O per Sq. Inch 376.3 68.2
Silicon Efficiency    
Power Dissipation    
     
Die Protection    
Package Type Leads Attached to Sub Bare Die Glob Top
Lid Type Ceramic Lids Plastic Lead Frame/ Plastic Lid
Attachment Method B-Stage Epoxy Epoxy
     
Pin Out Parameters    
Number and Types of Leads 26 J-leads 24 pin Header
     
Tests Required    
Environmental None None
Electrical Ambient Final Functional Ambient Final Functional
Test Program Development Customer Customer
Test Fixture Development APTA Customer

 

Industry Segment:
Medical
Part Description: Audio Unit RF Unit
Parent Product Behind the Ear(BTE) hearing aid/FM Receiver Combination Behind the Ear(BTE) hearing aid/FM Receiver Combination
Electrical Design: Customer Customer
Layout: APTA APTA
Circuit Size(X-Y) (inches) Irregular Irregular
Circuit Area (Sq. Inches) 0.36 0.4
     
Interconnect Parameters    
Substrate Technology: LTTT on Alumina LTTT on Alumina
Metall Layers 2 3
Conductor Material Platinum Silver Platinum Silver
Typical Geometries .004 lines/.004 spaces .004 lines/.004 spaces
Via Sizes .004 Round .004 Round
Through Hole Size 7 7
Via Quantity 59 192
Through Hole Quantity 57 71
'Vias per Square Inch/Layer 161.1 219.2
Integrated Resistors 25 10
Integrated Capacitors 0 0
     
Component Parameters    
Bare Die 4 15
Wire Bonds 21 46
Wire Types/Sizes 1 mil Gold 1 mil Gold
SMT Devices 22 34
Smallest Passive 0402 0402
Total I/Os 120 144
Total Components per Sq. Inch 141.7 147.5
Total I/O per Sq. Inch 333.3 360.0
Silicon Efficiency    
Power Dissipation    
     
Die Protection    
Package Type Circuit in Plastic Enclosure Circuit in Plastic Enclosure
Lid Type Bare Die Glob Top Bare Die Glob Top
Attachment Method NA NA
     
Pin Out Parameters    
Number and Types of Leads NA NA
     
Tests Required    
Environmental None None
Electrical Ambient Final Electrical Ambient Final Electrical-RF
Test Program Development Customer Customer
Test Fixture Development Customer/APTA Customer/APTA

 

Industry Segment:
Military
 
Part Description: 4 Channel multplexed 12 bit A/D Converter Commutation Driver
Parent Product Test Missiles Flir Night Vision
Electrical Design: Customer APTA
Layout: APTA APTA
Circuit Size(X-Y) (inches) 1.36x1.0  
Circuit Area (Sq. Inches) 1.36 1.29
     
Interconnect Parameters    
Substrate Technology: Multilayer Thick Film Single Layer Thick Film
Metall Layers 5 1
Conductor Material Gold Gold
Typical Geometries .010 lines/.010 Spaces .010 lines/.010 Spaces
Via Sizes .012X.010 Rectangular 0
Through Hole Size 10 mil 0
Via Quantity 1397 0
Through Hole Quantity 110 0
'Vias per Square Inch/Layer 221.6 0.0
Integrated Resistors 58 24
Integrated Capacitors 0 0
     
Component Parameters    
Bare Die 52 29
Wire Bonds 491 101
Wire Types/Sizes 1.0 mil Gold 1.0 mil gold/5.0 mil Alu
SMT Devices 22 0
Smallest Passive 0504 NM
Total I/Os 610 154
Total Components per Sq. Inch 97.1 41.1
Total I/O per Sq. Inch 448.5 119.4
Silicon Efficiency    
Power Dissipation    
     
Die Protection    
Package Type Hermetc Kovar Tub Leads Attached to Sub
Lid Type Kovar Plastic
Attachment Method Seam Sealed Epoxy Attach
     
Pin Out Parameters    
Number and Types of Leads 54 Gull Wing 10 Thru hole pins
     
Tests Required    
Environmental Full mil-883 None
Electrical Active Trim of 22 Rest and 3Temp Final ET Functional
Test Program Development APTA Customer
Test Fixture Development APTA APTA

 

Industry Segment:
Telecom
 
Part Description:    
Parent Product FiberOptic Switch FiberOptic Switch
Electrical Design: Customer Customer
Layout: APTA Customer
Circuit Size(X-Y) (inches) 1.54x0.525 .65x21
Circuit Area (Sq. Inches) 0.8085 0.1365
     
Interconnect Parameters    
Substrate Technology: Multilayer Thick Film Thin Film
Metall Layers 2 1
Conductor Material Gold NA
Typical Geometries .010 lines/.010 Spaces .001Lines/.001 Spaces
Via Sizes .012X.010 Rectangular NA
Through Hole Size 10 mil NA
Via Quantity 17 NA
Through Hole Quantity 68 NA
'Vias per Square Inch/Layer 52.6 NA
Integrated Resistors 44 0
Integrated Capacitors 0 NA
     
Component Parameters    
Bare Die 16 7
Wire Bonds 143 18
Wire Types/Sizes 0.7/1.0mil Gold 0.7/1.0mil Gold
SMT Devices 25 8
Smallest Passive 0805 306
Total I/Os 259 14
Total Components per Sq. Inch 105.1 109.9
Total I/O per Sq. Inch 320.3 102.6
Silicon Efficiency    
Power Dissipation    
     
Die Protection    
Package Type Kovar Tub Kovar Tub
Lid Type Kovar Kovar
Attachment Method Seam Seal Seam Seal
     
Pin Out Parameters    
Number and Types of Leads 26 DIP 14 DIP
     
Tests Required    
Environmental None None
Electrical None None
Test Program Development None None
Test Fixture Development None None

 

Industry Segment
Test and Measurement
 
Part Description: Cable Compensation Network Active Probe
Parent Product High Speed VLSI Test System Intelligent Probe for Logic Analyzer
Electrical Design: Customer Customer
Layout: APTA APTA
Circuit Size(X-Y) (inches) .35x.35 .86x.75
Circuit Area (Sq. Inches) 0.1225 0.645
     
Interconnect Parameters    
Substrate Technology: Two Sided Single Layer Thick Film LTTT on BeO
Metall Layers 2 6
Conductor Material Platinum Silver Gold
Typical Geometries .010 lines/.010 Spaces .005 lines/.005 spaces
Via Sizes   .004 Round
Through Hole Size 8 mil 0
Via Quantity   1032
Through Hole Quantity 8 0
'Vias per Square Inch/Layer 32.7 266.7
Integrated Resistors 30 10
Integrated Capacitors   10
     
Component Parameters    
Bare Die 0 2
Wire Bonds 0 58
Wire Types/Sizes NA 1.0 mil Gold
SMT Devices 18 10
Smallest Passive 0402 0402
Total I/Os 106 131
Total Components per Sq. Inch 391.8 49.6
Total I/O per Sq. Inch 865.3 203.1
Silicon Efficiency NA  
Power Dissipation    
     
Die Protection    
Package Type Substrate as LCC Elastomer Connector
Lid Type Ceramic Bare Die Glob Top
Attachment Method Epoxy Glob NA
     
Pin Out Parameters    
Number and Types of Leads 10 Lead LCC 15 Output Pads
     
Tests Required    
Environmental None None
Electrical Functional LCR Test Active Trim of Caps and Final ET
Test Program Development APTA APTA Active Trim/Customer FET
Test Fixture Development APTA APTA